changeset 107:47722b02b4d5

Fix long line in cache module
author Lewin Bormann <lbo@spheniscida.de>
date Sun, 09 Oct 2016 16:34:16 +0200
parents c081aa8e18ca
children cb744c4fbd54
files src/cache.rs
diffstat 1 files changed, 2 insertions(+), 2 deletions(-) [+]
line wrap: on
line diff
--- a/src/cache.rs	Sun Oct 09 16:23:28 2016 +0200
+++ b/src/cache.rs	Sun Oct 09 16:34:16 2016 +0200
@@ -156,8 +156,8 @@
 /// Based on a HashMap; the elements are linked in order to support the LRU ordering.
 pub struct Cache<T> {
     // note: CacheKeys (Vec<u8>) are duplicated between list and map. If this turns out to be a
-    // performance bottleneck, another layer of indirection™ can solve this by mapping the key to a
-    // numeric handle that keys both list and map.
+    // performance bottleneck, another layer of indirection™ can solve this by mapping the key
+    // to a numeric handle that keys both list and map.
     list: LRUList<CacheKey>,
     map: HashMap<CacheKey, CacheEntry<T>>,
     cap: usize,